1. Field of the Invention.
This invention relates to an improved method and apparatus for correcting flutter, otherwise known as timebase error of a television video or similar type of signal.
2. Description of the Prior Art.
Several devices, commonly known as timebase correctors, which correct flutter or timing errors are currently being manufactured. Many of these devices utilize digital memory along with analog to digital (A-D) and digital to analog (D-A) conversion of the signal being processed in order to facilitate use of the digital memory. One such invention is described in U.S. Pat. No. 3,860,952. Other inventions such as U.S. Pat. No. 3,763,317 utilize a high frequency carrier which is modulated by the video signal, the carrier may be delayed by various combinations of fixed and variable delay lines, and subsequently demodulated to recover a stable video signal.
With improvements in Charge Coupled Device (CCD) and Bucket Brigade Device (BBD) technology, analog shift register IC's such as those manufactured by Fairchild (Part No. CCD-321) and Plessy (Part No. MS 1003) are being used in new timebase correctors, such as the inventions disclosed in U.S. Pat. Nos. 3,959,815 and 4,150,395. The inventive concept of these products involves the use of a variable frequency clocking signal to the CCD device in order to change the delay time of the video signal being passed through the device in order to compensate for timing errors.
All of the above techniques, while being workable, have shortcomings. With the digital technique the cost of the A-D and D-A circuitry is very high. The modulated carrier systems utilize expensive delay lines and require the use of difficult to design and align modulator and demodulator circuitry. The variable frequency clocked CCD technique is not well suited for handling large timebase errors, and compensating for sin x/x frequency losses, which change as the CCD clocking frequency changes, can be very difficult.
One invention which can overcome all of the above problems is described in U.S. Pat. No. 3,931,638. This invention utilizes time multiplexing of two CCD analog delay lines thus taking advantage of the low power consumption and relative low cost of CCD's. In addition, the use of a clocking frequency which is locked to video synchronizing pulses will eliminate the sin x/x frequency loss problem associated with the variable frequency CCD approach. The above identified disclosure does suggest that more than two CCD devices can be utilized for improved error correction capability, however the disclosure does not make any mention of the problems which will arise, such as matching multiple devices, when such an improvement is made.
It should be noted here that the device disclosed in U.S. Pat. No. 3,931,638 is not capable of handling any timing errors on continuous signals with currently available CCD devices. With the currently available devices, it is not possible to read and write at the same time since only one clock input is available. Therefore with only two CCD's when one is filled it is not possible to start filling the other until the other is completely empty. In this situation the input signal will have to be stopped or else it will be missed. Of course it would be possible to arrange the timing of the system so that the filling of each CCD takes place during blanking since the sync and blanking periods can be reinserted on the output side of the CCD.
Two further inventions disclosed in U.S. Pat. Nos. 4,206,478 and 4,206,479 make use of special parallel transfer CCD devices for timebase correction, however these special devices are much more complex and therefore more costly to manufacture than the normal CCD shift register devices.
The above identified inventions will also suffer from the same matching problems when using multiple devices as will U.S. Pat. No. 3,931,638, which matching problems are not identified or otherwise addressed.